Last Updated： Aggregation Period:Feb 25, 2026～Mar 24, 2026
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1～30 item / All 49 items
High quality, low latency, power-saving IP Core
Providing a group of MPEG standard codecs as IP Cores with high quality, low latency, low power consumption, and a small footprint. Available in Intel FPGA and Xilinx versions.
Providing high-quality and high-performance IP core products for the storage industry! Supporting the development of ASSP products as well.
IntelliProp develops high-quality and high-performance IP core products and ASSP products for the storage industry. Since its establishment in 1998, the company has been providing competitive IP core products as a leading company in specialized fields such as SATA, SAS, PCIe/NVMe, NAND flash, security/encryption, and RAID technology in Longmont, Colorado, USA, where major companies in the storage industry gather. *For more details, please refer to the PDF document or feel free to contact us.*
It is an application layer equipped with an interface to the processor!
We would like to introduce the "NVMe Host Accelerator IP Core" that we handle. This product is an NVMe host IP core from IntelliProp that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) with 8 lanes. It also features queuing and issuing capabilities for NVMe commands, allowing you to use it as a solution for high-speed data access to NVMe target devices. 【Specifications (excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Supports automatic initialization using PCIe hard blocks ■ Compatible with third-party PCIe Root Complex IP cores ■ Number of queues is adjustable (up to 64K) ■ Maximum data buffer size of 1GB *For more details, please download the PDF or feel free to contact us.
It is designed to be compact so that the necessary space for the application can be secured on the FPGA.
We would like to introduce the 'CoaXPress IP Core' that we handle. The CoaXPress interface provides a series of IP cores and development frameworks for building FPGA-based transmitters. Additionally, the CXP core is compatible with AMD 7 series (and later), Intel Cyclone V devices (and later), and Microchip PolarFire series. 【Features】 ■ Minimizes development time ■ Achieves top-class performance with a minimal footprint ■ Ensures sufficient flexibility to customize designs ■ Receives all data output from video sensors to CXP PHY ■ Implements control channels according to CXP specifications *For more details, please download the PDF or feel free to contact us.
For engineers aiming for product development in the short to medium term! Compact and customizable.
We would like to introduce our "USB3 Vision IP Core." We provide a set of IP cores and development frameworks for building FPGA-based products using the USB3 Vision interface. It is also compatible with AMD 7 series devices (and later) and Intel Cyclone V devices (and later). 【Features】 ■ Minimizes development time while achieving top-class performance with a small footprint ■ Ensures sufficient flexibility to customize designs ■ Option to have the source code of the embedded USB3 Vision library running on the Cypress FX3 USB controller *For more details, please download the PDF or feel free to contact us.
Multiple independent data streams! You can choose the AES encryption key from 128 or 256 bits.
We would like to introduce the 'AES-GCM Encryption IP Core' that we handle. This is an AES-GCM (Galois Counter Mode) encryption IP core that enables users to perform encryption/decryption and authentication of packets or data streams. It supports AES-GCM encryption levels of 128 or 256 bits and is capable of data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. 【Specifications】 ■ AES encryption key selectable from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput *For more details, please download the PDF or feel free to contact us.
Helps connect MIPI sensors from various vendors to FPGA!
We offer the 'MIPI CSI-2 Receiver IP Core', which allows for easy camera design. It is provided as encrypted VHDL, and the VHDL source code is available as an option. Additionally, the MIPI CSI-2 receiver IP software library is provided as an object file, with the option to obtain it as C source code. 【Features】 ■ Compatible with AMD Artix7, Kintex7, Zynq7, and Ultrascale+ FPGAs ■ Comes with a complete reference design for S2I's MVDK equipped with Zynq7 or Ultrascale+ FPGA and IMX MIPI FMC module ■ Easy to port designs to other FPGA platforms *For more details, please download the PDF or feel free to contact us.
You can choose the AES encryption key from 128 or 256 bits! The encryption algorithm complies with FIPS-197.
We would like to introduce the 'AES-XTS Encryption IP Core' that we handle. This product is an AES-XTS encryption IP core that enables full disk encryption for storage devices. It supports AES-XTS encryption levels of 128-bit or 256-bit and allows encryption tailored to data transfer rates of SATA 6Gbps, SAS 12Gbps, and PCIe (NVMe) Gen4 x4 lanes. 【Specifications】 ■ FIPS-197 compliant AES-XTS algorithm ■ AES encryption key selectable from 128 or 256 bits ■ Configurable number of encoding/decoding pipelines ■ Independent management of encryption/decryption keys ■ Simultaneous support for encoding and decoding ■ Supports integer multiples of 16-byte data unit sizes *For more details, please download the PDF or feel free to contact us.
Configurable encoding/decoding block! Parallelized BCH encoder/decoder.
The "ECC with BCH Algorithm IP Core" is an IP core designed to add error detection/correction functionality using industry-standard BCH class error correction codes, preventing data loss or corruption over noisy and unreliable communication channels. If the BCH configuration is not covered, it can be customized to support a wide range of BCH codes. It can be used in a variety of applications, including data storage devices (SATA, SAS, FLASH), two-dimensional barcodes, satellite communication/telemetry, radio signal recording, wireless communication, high-speed modems such as ADSL and xDSL, and power line standards. 【Specifications】 ■ High bandwidth and low latency through parallel processing ■ Configurable encoding/decoding block structure ■ Configurable word length/block size ■ FIFO data interface of 32, 64, 128, or 256 ■ Parallelized BCH encoder/decoder *For more details, please download the PDF or feel free to contact us.
Compliant with SMPTE 2059-1/2! Hitless time synchronization is possible through line redundancy.
The "IP_SMPTE2059_SLV" is an IP core for slaves compliant with ST 2059-1/2. There are two types: the vPTPM (Master-Core) on the master side and the vPTPS (Slave-Core) on the slave side, which can be used individually, in multiples, or in combination. Additionally, it has ports for sending and receiving control packets from the MPU bus and is compatible with NMOS, among others. 【Features】 ■ Compliant with SMPTE 2059-1/2 ■ Counter output for PTS ■ 1PPS output ■ Serial output of time information ■ Capable of sending and receiving control packets using the MPU *For more details, please refer to the PDF documentation or feel free to contact us.
The video format supports 4K/HD/SD! You can manage Ethernet statistics.
The "IP_SMPTE2110" is an IP core compliant with ST 2110-10/20/30/40. It comes in two types: vEGSV (Egress-Core) for the transmission side and vIGSV (Ingress-Core) for the reception side. They can be used individually, in multiples, or in combination. Additionally, the number of SDI channels and Ethernet ports can be freely combined. 【Features】 ■ Compliant with SMPTE 2110-10/20/30 ■ Supports video formats 4K/HD/SD ■ SMPTE 2022-7 (Hitless support) ■ Capable of supporting control in-channel communication ■ Compatible with IPv4 and IPv6 *For more details, please refer to the PDF document or feel free to contact us.
Providing IEEE1588-2008 PTP time synchronization solutions as an IP core. Synchronizing devices on Ethernet (LAN) with nanosecond precision.
Oregano Systems offers timing synchronization solutions compliant with IEEE1588-2008 Precision Time Protocol as IP CORE. It provides syn1588 Clock_S for serial connection to external CPUs and syn1588 Clock_M for parallel connection, available in netlist or source code. Synchronization in the nanosecond range over Ethernet is possible. Support for 802.1AS will be available starting summer 2016.
This is an IP product that realizes high image quality and high performance for AI camera systems.
Compatible with Sony's IMX390 image sensor HDR functionality, it can support high-sensitivity cameras with low noise and a wide dynamic range even in harsh environments such as rain, fog, and backlighting. It can be utilized in products that require high visibility, such as mobility, safety support systems, and surveillance systems. Product introduction manufacturer website: https://www.dmprof.com/ja/products-and-services/ai-products/hardware/ip-core/zia-isp.html
FireCore is an IP core that integrates PHY and link layer controller (LLC) cores into a single IP product.
FireCore integrates the PHY and link layer requirements necessary for common 1394 devices into a single IP core. Based on the FireGate PHY IP core and FireLink LLC IP core, FireCore is designed to support data rates from S100 to S3200 and various host interfaces such as generic, OHCI, and OHCI (with AS5643 option). DapTechnology's new FireCore package offers unprecedented technical capabilities, features, flexibility, and options for customization and future expansion. Together with FireStack (DapTechnology's 1394 software stack), FireCore is designed to fully leverage the capabilities of the AS5643 extension. It aims to completely abstract the 1394 protocol layer and the AS5643 protocol layer, allowing implementers to focus entirely on system-level functionalities such as fault tolerance, fault isolation, and redundancy.
64-bit CPU architecture! It can access an address space significantly exceeding 4GB.
The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.
Seamlessly accelerate increasingly complex compute-intensive AI workloads!
The "Dynamic Neural Accelerator (DNA)" is a flexible deep learning inference IP core characterized by high computational power, ultra-low latency, and a scalable inference engine. While boasting excellent power efficiency compared to other standard processors, it achieves ultra-low latency for inference in streaming data. Please feel free to contact us if you have any inquiries. 【Features】 ■ Ultra-low latency AI inference IP core ■ Robust open-source MERA software framework ■ Compatible with both FPGA and ASIC/SoC (The photo and link below show an example of DNA mounted on the Bittware (Molex Japan) FPGA card IA420F.) *For more details, please refer to the link below, download the PDF, or contact us. Reference link: https://www.bittware.com/ja/ip-solutions/edgecortix-dynamic-neural-accelerator/
![[Siliconarts] Raytracing GPU IP](https://image.mono.ipros.com/public/product/image/a64/2001222186/IPROS14149370522694074335.png?w=280&h=280)
The world's first real-time Ray tracing & Path tracing GPU IP.
A fabless company that owns raytracing GPU IP and is planning to develop artificial intelligence models and AI processors for edge devices as a new business. For chip development, basic logic design is conducted internally, while backend design is primarily carried out through foundry design houses. [RayCore MC] - MIMD-based low-power high-performance real-time raytracing & path tracking GPU - Achieves real-time low-power raytracing functionality.
Compatible with OpenSSL's AES-256-CTR encryption mode! Multiple independent data streams.
The "AES-CTR Encryption IP Core" is an IP core for AES-CTR (Counter Mode) encryption that allows users to perform encryption/decryption of packets or data streams. It supports AES-CTR encryption levels of 128 or 256 bits and enables data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. Additionally, it is compatible with OpenSSL's AES-256-CTR encryption mode. 【Specifications】 ■ AES encryption key can be selected from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput ■ Compatible with OpenSSL's AES-256-CTR encryption mode *For more details, please download the PDF or feel free to contact us.
It can be easily integrated into SoCs such as HD TVs and AV receivers.
The HDMI receiver link IP core "SLISIHDMI" complies with the HDMI 1.3a standard, and when connected to the HDMI Receiver PHY IP SLIPHDMIR, it can most efficiently leverage the performance of the SLISIHDMIR HDMI Rx IP. Additionally, it is possible to customize the functions of the SLISIHDMIR HDMI Rx IP according to your requirements. For more details, please contact us.
OOB sequence and speed negotiation sequence support!
The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.
Error correction code with the option to add bit/byte interleaving function.
The "Reed-Solomon Encoder/Decoder" is an IP core for error correction coding/decoding using the Reed-Solomon method, which is used to improve communication quality in a wide range of fields such as wireless devices, xDSL modems, and digital TVs. It supports variable data block lengths. 【Features】 ■ Supports variable data block lengths ■ The number of check bits, primitive polynomial, and generator polynomial can be customized according to your requirements ■ Additional bit/byte interleaving functionality is also possible *For more details, please refer to the PDF document or feel free to contact us.
Mechatrolink communication macros can be implemented on intel-FPGA.
This is a soft IP that enables the implementation of the MECHATOROLINK-III communication protocol on FPGA. It flexibly accommodates the addition of various interfaces and peripheral circuits, which are features of FPGAs, and allows for easy design integration using the GUI of the Qsys system integration tool. The basic functionality of this IP is equivalent to Yaskawa Electric's JL-100/JL-102. It is easy to build an evaluation environment by combining the Macnica Sodia board with our SY-M3-03 board. High functionality and high-speed processing are achieved through cooperative operation between the ARM Cortex-A9 and user circuits (ARM is used when employing Intel FPGA SoC). * Operation has been confirmed on the Macnica Sodia-Cyclone V ST SoC evaluation board. ■ Supports C1 master/slave/multi-slave configurations ■ Netlist provided as a Soft-IP core ■ MECHATROLINK-III certification obtained
Support for integrating the Holt HI-6300 IP core into Vivado design and FPGA implementation.
In the aerospace industry, reliable data transmission is essential. Particularly in communication under harsh environments, the accuracy and stability of data become crucial. The HI-6300 IP core supports FPGA implementation and provides a solution to enhance the reliability of data transmission. This product demonstrates access to IP bus controller (BC), remote terminal (RT), and monitor (MT) functions using the Holt API library. 【Usage Scenarios】 - Data transmission in aerospace equipment - Development of communication systems using FPGA - Evaluation of the HI-6300 IP core 【Benefits of Implementation】 - Rapid integration into FPGA designs - Improved reliability of data transmission - Reduced development time
No need for complex memory cell configurations! We provide high-performance non-volatile memory at low manufacturing costs.
"TwinBit" is a non-volatile memory IP core that can be manufactured using standard logic processes. It is capable of over 100,000 write cycles across a wide range of processes, from the 0.18um generation to advanced 16nm generation and beyond. It provides high-performance non-volatile memory at a low manufacturing cost without requiring the complex memory cell configurations typical of conventional Flash memory. Customization is also available for various non-volatile memory core applications, ranging from 64-bit latch types to 2MByte code storage memory. 【Features】 ■ World-class smallest memory cell size ■ High-speed, low-power read operation ■ Low-voltage write operation ■ Built-in test circuits *For more details, please refer to the PDF document or feel free to contact us.
Achieving affordable and reliable shipping inspections! We support high quality and stable yields.
"PermSRAM" is an OTP non-volatile memory IP core that can be manufactured using standard logic processes. It provides non-volatile memory that can be written only once for a wide range of processes, from the 0.18um generation to advanced 28nm generations and beyond. Customization is possible for various non-volatile memory core applications, ranging from 64b latch types to 1MByte code storage memory. 【Features】 ■ World-class smallest area ■ Reverse engineering resistance ■ Low voltage writing ■ Equipped with test circuits ■ Automotive grade (guaranteed up to 150℃) *For more details, please refer to the PDF document or feel free to contact us.
Supports power modes (partial/slumber)! The DATA interface uses FIFO.
We would like to introduce our "FPGA/ASIC IP Core for SATA Device ADCI." This is an IP core for SATA devices that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It features an ADCI (Advanced Device Controller Interface) that allows for easy operation via processors/firmware, making it suitable for a wide range of SATA storage device solutions. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports Application layer, Transport layer, Link layer, and Phy layer, including ADCI ■ Supports OOB (Out of Band) ■ Uses FIFO for DATA interface *For more details, please download the PDF or feel free to contact us.
Supports automatic initialization using PCIe hard blocks!
The "NVMe-to-NVMe Bridge" is an NVMe bridge IP core that creates an NVMe protocol bridge using NVMe Host IP cores and NVMe Target IP cores. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. It can be used for purposes such as LBA remapping, data encryption, data compression, and endpoint aggregation. 【Specifications】 ■ Compliant with NVM Express 1.4 standard ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks ■ Automated command transmission and completion ■ Application layer with an interface to the processor *For more details, please download the PDF or feel free to contact us.
It can widely support systems that require a SATA host!
The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.
There are configurable settings that allow for trade-offs between core size and performance requirements!
The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.
It is equipped with an IEEE-754 compliant floating-point unit that enhances floating-point processing capabilities!
The "AndesCore N15/N15F" is a dual-issue superscalar AndesCore processor. It offers a performance of 5.41 CoreMark/MHz and comes with various configuration options such as MMU, cache, and local memory. Additionally, the 64-bit data bus for cache, local memory, and main bus provides the bandwidth necessary for instruction fetch and data access. 【Specifications】 ■ Dual-issue pipeline ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (N15F) ■ Memory Management Unit (MMU) for Linum ■ 64-bit AXI4/AHB/AHBx2 bus interface *For more details, please refer to the related links or feel free to contact us.
